This page is referenced from the PowerPc page - it might be worth making some general points and moving some of that discussion here. Some of it probably belongs here rather than there anyway, and I suspect this page is worth something by itself.

Perhaps simply some references to get started?

* http://www.google.co.uk/search?q=%22Risc+versus+Cisc%22
* http://www.google.co.uk/search?q=%22Risc+vs+Cisc%22

Besides, is it not the case that the Pentium IV chip is comprised of several ARM cores and a "skin"?

''RISC is having the ARM core. CISC is having multiple ARM cores and a load of frontend hardware to turn them into one logical processor with its own non-ARM ISA.''

This is over-simplification to the point of nonsense. SPARC and PowerPC are both RISC architectures.

(Then maybe SPARC and PowerPC aren't RISC anymore, despite what the earilest versions of the architectures were. But see the final line of this comment, below.)

''That is, assuming RISC and CISC mean anything anymore.''

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Many FpgaCpu''''''s are RISC, to make them small enough to fit on the FPGA.

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See

* ReducedInstructionSetComputer
* http://en.wikipedia.org/wiki/CPU_design
* http://en.wikipedia.org/wiki/RISC

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CategoryHardware